1. Field of Invention
The invention generally relates to a data converter and the method of conversion. More specifically, the invention relates to a serial-to-parallel data conversion circuitry that has an additional pre-register installed in a multi-phase clock architecture to maintain the number of required phase clock signals as same as the number of the width of the parallel data bits.
2. Related Art
High-speed serial transmissions have wide applications nowadays. In the future, they will be applied to both network data transmissions and data transmission within computer systems. Currently, the most common applications of the high-speed serial transmission include: 1394a data transmissions with a bandwidth of 400 Mbps, USB2.0 data transmissions with a bandwidth of 480 Mbps, Serial ATA data transmissions with a bandwidth of from 1.5 Gbps to 6 Gbpsxe2x80xa2Infiniband and 3GIO data transmissions with a bandwidth of 2.5 Gbps. Although all the above-mentioned high-speed serial transmissions adopt different data coding methods, the receiver of the serial data has to be able to always convert them into a parallel data.
At present, the circuit design for converting serial data to parallel data usually uses a shift register. A shift register is made up of a plurality of latch units, flip-flops (FF), connected in series to each other. As shown in FIG. 1, the serial data enter the shift register in order. Once the shift register collects full the serial data, the data stored by the FF 1 are output in parallel. Although this circuit is simple in design, serial data transmissions for high speed require improvement in the manufacturing technology in order to achieve the speed requirement of the shift register. To solve this problem, a multi-clock phase architecture was developed to replace the shift register one. In spite of the fact that this multi-clock phase architecture can effectively increase the conversion speed limitation of serial data, it at the same time demands more phase clock signals. If the parallel data output design in incorporated, this type of circuitry generally adopts the conversion structure with twice the width of the parallel data bits. With reference to FIG. 2, when one shift register receives serial data, another shift register outputs the parallel data. Nevertheless, the drawback of this design is that clock signals with twice the parallel data width and different phases are needed. Precision clocks are the key to the technical application.
An objective of the present invention is to provide a serial-to-parallel data conversion method, which under a multi-clock phase architecture only need to generate the number of phase clock signals with the same width as the parallel data.
As described before, the conventional conversion technology requires phase clock signals with twice the width of the parallel data in the multi-clock phase architecture and the precision clock signals under high-frequency operations are the key factor in the conversion technology. The circuit design becomes so complicated that the manufacturing cost also increases. Therefore, the present invention provides a solution to make serial-to-parallel data conversions that can operate at a high-frequency. In a preferred embodiment of the present invention, a serial-to-parallel data converter for converting a serial data into a n-bit parallel data, comprises: a latch circuit, comprised of a first data receiver and a second data receiver for storing the n-bit parallel data; a phase clock generator, generates n phase clocks corresponding to the n-bit parallel data in a conversion cycle and simultaneously latches the corresponding bits in the first data receiver and the second data receiver at each phase clock; and a selector, selects one of the first data receiver and the second data receiver to perform serial data conversion and the other receiver to output parallel data.
Another embodiment of the present invention further solves the problem that under high-frequency operations, the switching between different data receivers for serial data conversion and parallel data storage may result in incomplete parallel data reception. In this embodiment, the disclosed serial-to-parallel data converter for converting a serial data into a n-bit parallel data, comprises: a latch circuit, comprised of a first data receiver and a second data receiver for storing the n-bit parallel data; a phase clock generator, generates n phase clocks corresponding to the n-bit parallel data in a conversion cycle and simultaneously latches the corresponding bits in the first data receiver and the second data receiver at each phase clock; a pre-register, stores the first m bits of the parallel data in advance in each conversion cycle and shifts the pre-stored first m bits back to the first data receiver and the second data receiver before each conversion ends; and a selector, switches between the first data receiver and the second data receiver to perform serial data conversion and the other receiver to output parallel data.
The above embodiment utilizes an additional pre-register to store in advance the bits that may be lost when the selector switches, so that the data receiver can receive the complete parallel data without any mistakes and the number of phase clocks is equal to the width of the bits in the parallel data.